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MTC20136
ADSL TRANSCEIVER CONTROLLER
Dedicated controller for use with ADSL transceiver chips MTC20134, MTC20135 and MTC20455 - Performs ADSL control functions : - Initialization procedure - Line monitoring during operation - Rate adaptive modes
PQFP144 LFBGA160 ORDERING NUMBERS: Part number MTC20136PQ- l1 MTC20136MB-I1 Package 144 pin PQFP 160 pin LBGA Temp. -40 /+85C -40 /+85C

Supports the modem control interface protocol (CTRLE) Embedded high speed ARM microcore Glueless connection to MTC20135 and MTC20455 Parallel or serial modem control interface (CTRLE) for glueless connection to management entities Embedded UART Supports code download External Bus Interface for 8 and 16-bit FEPROM and 16-bit SDRAM 144 pins PQFP
Can also be ordered using kit number MTK20131 or MTC20455
DESCRIPTION The MTC20136 is a dedicated controller chip, specifically designed to control operations of the STMicroelectronics DynaMiTe chipset. The MTC20136 offers direct glueless interfaces to the MTC20135 and MTC20455 DMT/ATM transciever and implements a complete control interface for parameters and commands exchange between transceiver and system management. All real time ADSL-related functions (including EOC processing) are completely handled by the MTC20136.
Figure 1. Block Diagram
Microcontroller ARM Microcore ROM RAM
MTC20136
MTC-20135 or MTC-20455
External Bus Interface
SDRAM
Peripherals TIMER UART Parallel I/O
CTRLE Data buffer Interface Logic
CTRLE
Local Bus
FEPROM (optional)
8 data 9 address RS232
February 2004
General Purpose I/Os
Control Bus
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Functional Description Figure 1 is showing the global block diagram of the MTC20136. The functions can be grouped into the following: - Microcontroller - External Bus Interface - Control Interface (CTRLE) - Peripherals - Miscellaneous Microcontroller The microcontroller block includes an ARM-based microcore and its associated internal memory. 16 Kbytes on internal RAM and 128 x 32-bit words of ROM are foreseen. The ROM essentially contains the boot sequence needed for code download at startup. The use of the ROM by the microcore is defined by the state of the TROM pin during reset. External Bus Interface The External Bus Interface extends the internal microcontroller bus for connection of external devices. In particular, the bus is used to connect to the MTC20135 or MTC20455 modem chip and to external SDRAM (and optional FEEPROM). The CTRLE functional block implements the ADSL modem command and data buffer and the interface logic supporting the physical interfaces of the CTRLE. Peripherals The peripherals block includes two UARTS for RS232 interfacing to external systems and two general = purpose parallel I/O lines. Miscellaneous This includes the clock circuitry, reset circuitry, test functions and configuration control signals. CTRLE Interfaces External Bus Interface The external bus interface (EBI) provides a glueless interface to 8 and 16-bit asynchronous Flash EEPROM, 16 bit SDRAM devices and to slave devices with an i960-like 16 bit bus interface with multiplexed address and data (as available on DynaMiTe chips). The EBI provides two chip selects (E_nCS[1:0]) to be used for memory access (SRAM-like), one dedicated SDRAM chip select ((E_nCS_S) and four chip selects (E_nCS[7:4]) to be used for access to ADSL slave devices. The chip selects all correspond to a fixed 1Mbyte memory region in the microcontroller memory map, except for SDRAM access.
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PIN LAYOUT Functional Pin Summary The signals hereunder are grouped per functional interface. Figure 2. Pin functional description and type per interface
NTRST TCK TDI TMS IDDQ T_REQA T_REQB notCS[7:0] E_A[19:16] E_A[15:0] E_D[15:0] C_clk C_A[8:0] C_notCS C_Mode[1:0] C_notWr C_notRd TROM EIT[3:0] CLK_E RESETN RSRXD2 RSTXD2
JTAG Interface
TDO
Test Interface
T_ACK
E_CLK E_ALE EBI Interface E_nRDY E_nWEO E_nWE1 C_D[7:0] C_notint C_notRdy
CTRL-E Interface
Misc
Peripherals
Boot_M[1:0] RSRXD1 RSTXD1 PA1 PA0
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The table below describes the pins, organized per interface. Some of these pins have a multiple functionality. In this case both functionalities are mentioned.
Name External Bus Interface E_A[19:16] E_A[15:0] E_D[15:0] E_CLK E_ALE E_nCS_0 E_nCS_1 E_nCS_S E_nCS_4 E_nCS_5 E_nCS_6 E_nCS_7 E_nRDYRCV E_nOE E_nWE0 E_nWE1 Clock Bus Interface CLK_IN Parallel Port Interface PA[0] PA[1] UART1 Interface RSTXD1 RSRXD1 UART2 Interface RSTXD2 RSRXD2 Interrupt Interface EIT_0 EIT_1 EIT_2 EIT_3 JTAG Interface nTRST TCK TDI TMS TDO Reset Interface RESETN Boot Interface TROM I Boot from ROM select I Reset signal (Active High) I-PU I-PU I-PU I-PU O Reset JTAG interface JTAG clock Test Data In Test Mode Select Test Data Out I I I I External interrupt lines External interrupt lines External interrupt lines External interrupt lines O I Serial TX port Serial RX port O I Serial TX port Serial RX port I/O I/O Port A bit[0] Port A bit[1] I MTC20136 Master clock O I/O I/O O O O O O O O O O I O O O Address bus MSBs Address bus LSBs / Testbus MSBs Data bus / Testbus LSBs EBI clock (ASIC Access) Address latch enable (ASIC Access) Chip select signal (Memory Bank 0) Chip select signal (Memory Bank 1) Chip select signal (SDRAM) Chip select signal (ASIC 1) Chip select signal (ASIC 2) Chip select signal (ASIC 3) Chip select signal (ASIC 4) Data acknowledge Output enable Write enable LSB / W/notR indication Write enable MSB I/O Type Description
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Name Boot_M0 Boot_M1 C_A[8:0] C_D[7:0] C_nCS C_nInt C_mode[1:0] C_nWr C_nRd C_nRdy C_clk I/O I/O I IO I OD I I I OZ I I/O Type Description Download Mode .UART BaudRate. (Auto adjust or 9600 Bps). Download Mode Select (CTRL-E or UART1) Address bus (5 V tolerant) Data bus (5 V tolerant) Chip select (5 V tolerant) Ctrl-E external interrupt Ctrl-E interface bus mode (5 V tolerant) Write indication (5V tolerant) Read indication (5V tolerant) Ready indication Serial Input clock (5V tolerant) Ctrl-E Interface (Parallel mode only described - see above for Serial Mode)
I I-PU I-PD I-TTL O OZ OD IO
= = = = = = = =
Input, CMOS levels Input with pull-up resistance, CMOS levels Input with pull-down resistance, CMOS levels Input TTL levels Push-pull output Push-pull output with high-impedance state Open Drain output input / Tri-state Push-pull output
PQFP144 Pin Configuration (Default Value between ( ))
Pin# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Name E_A14 E_A15 E_A16 E_A17 VDD VSS E_A18 E_A19 EIT0 EIT1 VDD VSS EIT2 EIT3 I_MODE E_CLK E_ALE VDD EBI Address EBI Address EBI Address EBI Address VDD VSS EBI Address EBI Address External Interrupt In - 0 External Interrupt In - 1 VDD VSS External Interrupt In - 2 External Interrupt In -3 Tracking ICE Mode Select (0) EBI Clock Out EBI ALE VDD Function
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PQFP144 Pin Configuration (continued) (Default Value between ( ))
Pin# 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Name VSS E_nRDYRCV E_nWE0 E_nWE1 E_notCS_4 VDD VSS Boot_M0 Boot_M1 PA0 PA1 TROM VDD VSS T_REQA T_REQB T_ACK IDDQ RESETN TDI TDO VDD VSS TMS nTRST TCK RSTXD1 RSRXD1 RSTXD2 VDD VSS RSRXD2 TESTSE SCAN_CLK C_nInt VDD VSS CLK_IN VSS C_nRdy C_nRd VDD VSS EBI Ack in EBI Write Enable EBI Write Enable EBI ASIC ChipSelect VDD VSS BootMode Select BootMode Select General Purpose IO General Purpose IO Boot Mode Select VDD VSS Reserved for test (0) Reserved for test (0) Reserved for test Reserved for test (0) RESET (Active Low) JTAG Interface JTAG Interface VDD VSS JTAG Interface JTAG Interface JTAG Interface UART port 1 - TX UART port 1 - RX UART port 2 - TX VDD VSS UART port 2 - RX Test Scan Enable Test Scan Clock CTRL-E Interrupt VDD VSS Master Clock In VSS CTRL-E Interface CTRL-E Interface VDD Function
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PQFP144 Pin Configuration (continued) (Default Value between ( ))
Pin# 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 Name VSS C_nWr C_Mode0 C_Mode1 C_notCS C_CLK VDD VSS C_D0 C_D1 C_D2 C_D3 C_D4 C_D5 C_D6 VDD VSS C_D7 C_A0 C_A1 C_A2 C_A3 C_A4 VDD VSS C_A5 C_A6 C_A7 C_A8 VDD VSS I_BP I_DBGRQ notCS_7 notCS_6 notCS_5 VDD VSS E_nCS_2 E_nCS_1 E_nCS_0 E_nOE VSS CTRL-E Interface CTRL-E Interface CTRL-E Interface CTRL-E Interface CTRL-E Interface VDD VSS CTRL-E Interface CTRL-E Interface CTRL-E Interface CTRL-E Interface CTRL-E Interface CTRL-E Interface CTRL-E Interface VDD VSS CTRL-E Interface CTRL-E Interface CTRL-E Interface CTRL-E Interface CTRL-E Interface CTRL-E Interface VDD VSS CTRL-E Interface CTRL-E Interface CTRL-E Interface CTRL-E Interface VDD VSS Reserved (0) Reserved (0) EBI - ASIC Chip Select EBI - ASIC Chip Select EBI - ASIC Chip Select VDD VSS EBI - SDRAM Chip Select EBI - SRAM Chip Select EBI - FLASH Chip Select EBI - OE Function
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PQFP144 Pin Configuration (continued) (Default Value between ( ))
Pin# 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 Name E_D15 VDD VSS E_D14 E_D13 E_D12 E_D11 E_D10 E_D9 VSS VDD E_D8 E_D7 E_D6 E_D5 E_D4 VDD VSS E_D3 E_D2 E_D1 E_D0 E_A0 VDD VSS E_A1 E_A2 E_A3 E_A4 VDD VSS E_A5 E_A6 E_A7 E_A8 E_A9 VDD VSS E_A10 E_A11 E_A12 E_A13 EBI Data VDD VSS EBI Data EBI Data EBI Data EBI Data EBI Data EBI Data VSS VDD EBI Data EBI Data EBI Data EBI Data EBI Data VDD VSS EBI Data EBI Data EBI Data EBI Data EBI Address VDD VSS EBI Address EBI Address EBI Address EBI Address VDD VSS EBI Address EBI Address EBI Address EBI Address EBI Address VDD VSS EBI Address EBI Address EBI Address EBI Address Function
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LFBGA160 Pin Configuration
Pin# C4 B2 D4 C3 C2 E3 D3 D2 E4 E2 E1 F3 F4 F1 F2 G3 H1 G4 G2 H3 H4 H2 J3 K2 J4 J2 K3 K4 L2 L3 M2 M3 L4 N2 N3 N1 P1 P2 M4 P3 N4 M5 P4 Name E_A14 E_A15 E_A16 E_A17 VDD VSS E_A18 E_A19 EIT0 EIT1 VDD VSS EIT2 EIT3 I_MODE E_CLK E_ALE VDD VSS E_nRDYRCV E_nWE0 E_nWE1 E_notCS_4 VDD VSS Boot_M0 Boot_M1 PA0 PA1 TROM VDD VSS T_REQA T_REQB T_ACK IDDQ RESETN TDI TDO VDD VSS TMS nTRST EBI Address EBI Address EBI Address EBI Address VDD VSS EBI Address EBI Address External Interrupt In - 0 External Interrupt In - 1 VDD VSS External Interrupt In - 2 External Interrupt In -3 Tracking ICE Mode Select (0) EBI Clock Out EBI ALE VDD VSS EBI Ack in EBI Write Enable EBI Write Enable EBI ASIC ChipSelect VDD VSS BootMode Select BootMode Select General Purpose IO General Purpose IO Boot Mode Select VDD VSS Reserved for test (0) Reserved for test (0) Reserved for test Reserved for test (0) RESET (Active Low) JTAG Interface JTAG Interface VDD VSS JTAG Interface JTAG Interface Function
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LFBGA160 Pin Configuration (continued)
Pin# N5 L5 P5 M6 N6 P6 L6 N7 P7 M7 L7 P8 N8 M8 L8 N9 M9 P10 N10 L9 P11 M10 N11 P12 L10 N12 P13 M11 N13 N14 P14 M12 M14 M13 L11 L14 L13 L12 K14 K11 K13 J14 K12 Name TCK RSTXD1 RSRXD1 RSTXD2 VDD VSS RSRXD2 TESTSE SCAN_CLK C_nInt VDD VSS CLK_IN VSS C_nRdy C_nRd VDD VSS C_nWr C_Mode0 C_Mode1 C_notCS C_CLK VDD VSS C_D0 C_D1 C_D2 C_D3 NOT CONNECTED C_D4 C_D5 C_D6 VDD VSS C_D7 C_A0 C_A1 C_A2 C_A3 C_A4 VDD VSS CTRL-E Interface CTRL-E Interface CTRL-E Interface VDD VSS CTRL-E Interface CTRL-E Interface CTRL-E Interface CTRL-E Interface CTRL-E Interface CTRL-E Interface VDD VSS JTAG Interface UART port 1 - TX UART port 1 - RX UART port 2 - TX VDD VSS UART port 2 - RX Test Scan Enable Test Scan Clock CTRL-E Interrupt VDD VSS Master Clock In VSS CTRL-E Interface CTRL-E Interface VDD VSS CTRL-E Interface CTRL-E Interface CTRL-E Interface CTRL-E Interface CTRL-E Interface VDD VSS CTRL-E Interface CTRL-E Interface CTRL-E Interface CTRL-E Interface Function
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LFBGA160 Pin Configuration (continued)
Pin# J11 H14 J13 J12 H11 H13 H12 G11 F14 G13 G12 E14 F11 F13 F12 E11 E13 E12 C14 D11 D13 B14 D12 A14 C13 B13 C11 C12 B12 D10 B11 A11 C10 B10 A10 D9 C9 A9 B9 D8 B8 C8 D7 Name C_A5 C_A6 C_A7 C_A8 VDD VSS I_BP I_DBGRQ notCS_7 notCS_6 notCS_5 VDD VSS E_nCS_2 E_nCS_1 E_nCS_0 E_nOE E_D15 VDD VSS E_D14 E_D13 E_D12 E_D11 E_D10 E_D9 VSS VDD E_D8 E_D7 E_D6 E_D5 E_D4 VDD VSS E_D3 E_D2 E_D1 E_D0 E_A0 VDD VSS E_A1 CTRL-E Interface CTRL-E Interface CTRL-E Interface CTRL-E Interface VDD VSS Reserved (0) Reserved (0) EBI - ASIC Chip Select EBI - ASIC Chip Select EBI - ASIC Chip Select VDD VSS EBI - SDRAM Chip Select EBI - SRAM Chip Select EBI - FLASH Chip Select EBI - OE EBI Data VDD VSS EBI Data EBI Data EBI Data EBI Data EBI Data EBI Data VSS VDD EBI Data EBI Data EBI Data EBI Data EBI Data VDD VSS EBI Data EBI Data EBI Data EBI Data EBI Address VDD VSS EBI Address Function
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LFBGA160 Pin Configuration (continued)
Pin# B7 A7 C7 D6 A6 B6 C6 A4 D5 B5 A3 C5 B4 A2 B3 B1 Name E_A2 E_A3 E_A4 VDD VSS E_A5 E_A6 E_A7 E_A8 E_A9 VDD VSS E_A10 E_A11 E_A12 E_A13 EBI Address EBI Address EBI Address VDD VSS EBI Address EBI Address EBI Address EBI Address EBI Address VDD VSS EBI Address EBI Address EBI Address EBI Address Function
External pins E_D[15:0] E_A[19:0] nCS[7:4] E_CLK ALE nRDYRCV nOE nWE0 nWE1 16 bit data, multiplexed address/data 20 bit address (including commands for SDRAM) external chip select external clock Address Latch Enable Ready/Recover driven by selected device together with external pull-up output enable Write enable for LSB byte lane E_D[7:0] Write enable for MSB byte lane E_D[15:8]
These physical pins are used for different logical functions, depending on the external device which is accessed. The correspondance between physical and logical functions is given in Table 1 Table 1.
Pin Name E_A [19] E_A [18] E_A [17] E_A [16] MTC20135, MTC20455 access function SDRAM access function S_nRAS S_nCAS S_DQM0 S_DQM1 SRAM/FEPROM access function E_A [19] E_A [18] E_A [17] E_A [16]
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Table 1. (continued)
Pin Name E_A [15:0] E_D [15:0] E_nCS [1:0] E_nCS [7:4] E_nCS_S E_Clk E_ALE E_nRDYRCV E_nOE E_nWE0 E_nWE1 MTC20135, MTC20455 access function AD [15:0] nCS [7:4] E-Clk ALE nRDYRCV W/nR SDRAM access function S_A [11:0] S_Q [15:0] S_nCS S_Clk S_nWE SRAM/FEPROM access function E_A [15:0] E_D [15:0] E_nCS [1:0] E_nOE E_nWE0 E_nWE1
Memory map modes Three modes are defined : a) Normal mode: The internal RAM is mapped in the lower part of memory. This is the normal operating mode, it allows maximum speed access to exception vectors. b) Normal boot mode: If the TROM external pin is high at reset, the MTC20136 boots from an external FEPROM. c) Internal boot mode: If the TROM external pin is low at reset, the MTC20136 boots from its internal ROM. This mode can be used to perform code download from a host. Boot modes are used at RESET time. Boot_M0 andBoot_M1 on pin 26 and 27 conrol the port to be used for downloading the code into the SDRAM after Bootup. This when TROM is low.
Boot_M1 (Pin27) 0 1 1
Boot_M0 (Pin26) 1 0 1 9600 Bps via serail port 1 Par. CTRL-E Par.CTRL-E
MTC20135, MTC20455 access The MTC20136 directly connects to the MTC20135 without glue logic. Following features are provided for MTC20135 access : - 16 bit multiplexed address/data bus giving 64Kbyte address space per MTC20135. - synchronous ready-controlled operation - control signals : nCS[4:7], E_CLK, ALE, W/nR, nRDYRCV - Little endian byte ordering on 16 bit bus - nRDYRCV timeout mechanism The timing diagram of the access to the MTC20135 or MTC20455 is shown in figure 3:
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Figure 3. Access to MTC20135, MTC20455
Ta E_CLK notCSi ALE EBI E_D notRDYRCV W/notR Read Access Write Access Add 1 Din Add 2 Dout Tw Td Tr Ti Ta Tw Td Tr
SDRAM The SDRAM interface allows a glue-less interconnection of 1 SDRAM. Following features are provided for SDRAM access. - 16 bit databus and 12 bit address bus. - control signals : S_nCS, S_nRAS, S_nCAS, S_nWE, S_DQM[1:0 Control signal timing All SDRAM actions are triggered at the rising edge of its clock. Timing diagrams for a burst of four 16-bit accesses to 16-bit SDRAM (Figure 3 and Figure 4) show the basic behavior of the control signals. Figure 4. SDRAM read access (CAS latency = 3; Burst length = 4)
S_clk S_nCS S_nRAS S_nCAS S_nWE S_DQM[1:0] S_A[11:0] S_Q[15:0] EAact EArw EApre
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Figure 5. SDRAM write access (CAS latency = 3; Burst length = 4)
S_clk S_nCS S_nRAS S_nCAS S_nWE S_DQM[1:0] S_A[11:0] S_Q[15:0] EAact EArw EApre
Memory Following features are provided for memory access (SRAM or FEPROM) : - 16 bit databus and 20 bit address bus giving 1Mbyte address space per chip select - control signals : E_nCS[0:1], E_nOE, E_nWE0, E_nWE1 - setup and wait state insertion - 8, 16 and 32 bit access by MTC20136 to 8 or 16 bit memory according to little endian convention Figure 6. EBI memory access (32-bit Word R/W to 16 bit memory), maximum speed timing
E_nCSi E_nOE E_nWEO E_nWE1 E_A[19:2] E_A[1:0] E_D[15:0] A1[19:2] 00 10 00 LSB A2[19:2] 10 MSB EBI
LSB MSB
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EBI Interface Timing All timing parameters are specified at a load of 100 pF, all the electrical levels are CMOS compatible. Table 2. All signals
Symbol
tr,tf
Parameters Rise and Fall time (10% - 90%) Input load Output load
Min
Typ
Max 3 10 100
Unit ns pF pF
Ci Co
Table 3. EBI signal timing with respect to E_CLK
Symbol
Tdh Tds T
Parameters Data input hold time from E_CLK Data input setup time to E_CLK Data/Address output valid/tri-state delay from E_CLK ALE delay from E_CLK notOE delay from E_CLK notWEi delay from E_CLK (falling edge) W/notR delay from E_CLK notCSi delay from E_CLK
Min 3 10
Max
Unit ns ns
dd
10 6 6 6 3 3 10 10
ns ns ns ns ns ns
Twrd Toed Twed Twrd Tcsd
CTRLE The Ctrl-E interface is an ADSL-oriented mailbox system to exchange control and status messages between MTC20136 and an external controller. It consists of a mailbox and a physical interface. The mailbox has two 8-bit command registers to pass commands from the MTC20136 internal controller bus (ASB) to Ctrl-E (RxCommand) and from Ctrl-E to ASB (TxCommand), and two status registers (RxComAv and TxComAv) to indicate the status of the command register. Data associated with a command can be exchanged using a common CtrleDataBuffer. A hardware semaphore mechanism is provided to allow control of data consistency of the CtrleDataBuffer. Figure 7. Ctrl-E interface controller principle
RX TX Ctrl-E Mailbox CtrleDataBuffer ASB (512*8 bit dual port RAM) Semaphore RxComAv TxComAv RxCommand TxCommand To ITController Ctrlelnt0 Mailbox Interrupt controller Ctrlelnt1 MRd MWr MA[8:0] MD[7:0] MQ[7:0] Ctrl-E Serial Interface I/O Ctrl-E physical interface
D_SELctrle
Generic Parallel Interface
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The Ctrl-E physical interface between the mailbox and an external controller can be used in one of two modes: as a dedicated serial bus interface or as a generic parallel bus interface. Selection between serial and parallel mode is done with an external mode strap, IO pins are shared. Ctrl-E Mailbox The Ctrl-E Mailbox occupies a 512 byte memory map accessible by the Ctrl-E physical interface and by the ASB bus. The mailbox memory map is given in Table 4. An external interrupt can be generated by the Mailbox interrupt controller. A full description of the CTRLE protocol and use of the CTRLE mailbox is available in the "CTRLE Interface Specifications" documents, available separately. Table 4. Ctrl-E controller memory map:
Field TxCommand RxCommand TxComAv RxComAv Semaphore CtrleDataBuffer Acc RW RW RW RW PV RW Mailbox Address MA[8:0] 000h 001h 002h 003h 004h 005h-1FFh Size(bit) 8 8 1 1 2 8 Initial 00h 00h 0b 0b 00b 00h Function Command written by Ctrl-E, read by ASB Command written by ASB, read by Ctrl-E 1-bit register : 1 if TX command available 1-bit register : 1 if RX command available Semaphore for access to written by ASB, read by Ctrl-E 507x8 bit data buffer
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Ctrl-E Semaphore A simple semaphore mechanism is provided to allow control of the data consistency of the CtrleDataBuffer. One mailbox address is defined as a two-bit semaphore register protected by control logic to prevent unallowed write accesses to this register. Before the databuffer is read or written by one of the two interfaces (ASB or Ctrl-E) this interface should perform a 'P-operation' on the semaphore. After a read or write of the databuffer the interface should do a 'V-operation' releasing the semaphore. P and V operations are performed by write and read accesses to the semaphore register. The semaphore will be updated as shown in Table 5. Each semaphore operation (P or V) consists of two consecutive actions that don't have to be atomic : a)Write the correct value to the semaphore address (see Table 5) b)Read the value in the semaphore address. If the value read is different from the value writen the P or V operation was not succesfull and should be tried again. Table 5. Semaphore P and V operations: new value after write by ASB or Ctrl-E
semaphore operation originator write value previous semaphore value semaphore free 00b P ASB Ctrl-E V ASB Ctrl-E
01 11 00 00
semaphore taken by ASB 01b 01b 01b 00b 01b
Ctrl-E 11b 11b 11b 11b 00b
b b b b
01b 11b 00b 00b
The databuffers can be accessed without using the semaphore mechanism if data consistency is guaranteed in another way. If other values are written to the semaphore address than the values listed the write will not be performed. Ctrl-E Physical Interface Two parallel bus modes are defined to support both Motorola-compatible and Intel-compatible timing and control signals. This interface specification is compliant to Utopia Level 2 Parallel Management Interface. Selection of the Ctrl-E physical interface bus mode is done with the C_Mode[1:0] input pins : Table 6. Bus mode selected with C_Mode[1:0] inputs
C_Mode[1] 0 0 1 1 C_Mode[0] 0 1 1 0 Description Motorola-type parallel interface Intel-type parallel interface Reserved Reserved
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Generic Parallel Interface The two parallel bus modes differ only in the definition of 3 control signals: busmode 0 provides a read/ write selector, a data strobe and a ready acknowledge. Busmode 1 provides a read strobe, a write strobe and a ready acknowledge. The signal definition is shown in following table: Table 7. Ctrl-E interface signals in parallel interface modes
Signal name C_A[8:0] C_D[7:0] C_notCS C_notInt Type I IO I OZ address bus byte wide bidirectional data bus chip select Interrupt output, derived from CtrleInt1 signal from Mailbox : low when CtrleInt1 is low, else tri-stated 00b read access if 1, write access if 0 Data Strobe Bus cycle ready indication, indicates that data on bus can be sampled or removed 01b write cycle indication read cycle indication Bus cycle ready indication, indicates that data on bus can be sampled or removed, same as in mode 0 Function PIN C_A[8:0] C_D[7:0] C_notCS C_notInt
Mode 0 : Motorola-compatible mode C_Mode[1:0] C_Rd/notWr C_notDS C_notDtAck I I I OZ C_Mode[1:0] C_notWr C_notRd C_notRdy
Mode 1 : Intel-compatible mode C_Mode[1:0] C_notWr C_notRd C_notRdy I I I OZ C_Mode[1:0] C_notWr C_notRd C_notRdy
Write cycle timing Figure 8. Ctrl-E interface: write cycle timing in parallel modes 0 and 1
t1 C_A[8:0] C_D[7:0] C_notCS C_Rd/notWr C_notDS C_notDtAck t6 C_notWr C_notRd C_notRdy Mode 1 t3 t7 Mode 0 t2 t4 t8 t9 t5
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Table 8. write cycle timing in parallel modes 0 and 1
Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 Description C_A Setup to C_notDS (C_notWr) low C_notCS, C_Rd/notWr setup to C_notDS (C_notWr) low C_notDS (C_notWr) pulse width C_D setup to C_notDS (C_notWr) high C_A, C_D hold from C_notDS (C_notWr) high C_notDtAck (C_notRdy) valid from C_notDS (C_notWr) low C_notDtAck (C_notRdy) tri-state from C_notDS (C_notWr) high C_notCS, C_Rd/notWr hold from C_notDS (C_notWr) high C_notCS high to C_notCS Low 0 100 Min 0 0 215 15 5 15 15 Max Unit ns ns ns ns ns ns ns ns ns
Read cycle timing Figure 9. Ctrl-E interface: read cycle timing in parallel modes 0 and 1
t1 C_A[8:0] t9 C_D[7:0] C_notCS C_Rd/notWr C_notDS C_notDtAck t6 C_notRd C_notWr C_notRdy Mode 1 t3 t7 Mode 0 t2 t4 t8 t10 t11 t5
Table 9. read cycle timing in parallel modes 0 and 1
Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 Description C_A Setup to C_notDS (C_notRd) low C_notCS, C_Rd/notWr setup to C_notDS (C_notRd) low C_notDS (C_notRd) pulse width C_D valid from C_notDtAck (C_notRdy) low C_A, hold from C_notDS (C_notRd) high C_notDtAck (C_notRdy) valid from C_notDS (C_notRd) high C_notDtAck (C_notRdy) tri-state from C_notDS (C_notRd) high C_notCS, C_Rd/notWr hold from C_notDS (C_notRd) high Data tri-state from C_notDS (C_notRd) high Data tri-state from C_notCS high C_notCS high to C_notCS low (Min. time between 2 Accesses) 10 90 5 100 100 15 0 15 10 Min 0 0 215 10 Max Unit ns ns ns ns ns ns ns ns ns ns ns
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MTC20136
Peripherals UART Two identical UARTs are implemented in MTC20136. They offer similar functionality to the standard 16C550 device. They can support bit rates of up to 115.2 K bps and contain two 16 byte FIFOs for receive and transmit. General purpose I/Os Four pins are available for general purpose IOs, two are used as inputs to specify the boot configuration and two are output under SW control. The latter can be used for instance to drive external LEDs. Reset The MTC20136 has an asynchronous, active-low reset pin. An external clock is required to leave the reset state. Clock The MTC20136 is operated from the 35.328MHz Master clock, also used by the other DynaMiTe chips. ELECTRICAL SPECIFICATIONS Generic The values presented in the following table apply for all inputs and/or outputs unless specified otherwise. Specifically they are not influenced by the choice between CMOS or TTL levels. Table 10. IO buffers generic DC characteristics
DC Electrical Characteristics All voltages are referenced to VSS, unless otherwise specified, positive current is towards the device Symbol IIN IOZ IPU IPD RPU RPD Parameter Input leakage current Tristate leakage current Pull up current Pull down current Pull up resistance Pull down resistance Test Conditions VDD, no pull up/pull down VIN = VSS, VDD, no pull up/pull down VIN = VSS VIN = VDD VIN = VSS VIN = VDD VIN = VSS, Min -1 -1 -25 25 -66 66 50 50 Typ Max 1 1 -125 125 Unit A A A A kOhm kOhm
Table 11. IO buffers dynamic characteristics
DC Electrical Characteristics, important for transient but measured at (near) DC All voltages are referenced to VSS, unless otherwise specified, positive current is towards the device Symbol CIN dI/dt Ipeak COUT Parameter Input capacitance Current derivative Peak current Output capacitance (also bidirectional and tristate drivers) Test Conditions @f = 1MHz 8 mA driver, slew rate control 8 mA driver, no slew rate control 8 mA driver, slew rate control 8 mA driver, no slew rate control @f = 1MHz 23.5 89 85 100 7 Min Typ Max 5 Unit pF mA/ns mA/ns mA mA pF
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MTC20136
Input/Output CMOS Generic Characteristics The values presented in the following table apply for all CMOS inputs and/ or outputs unless specified otherwise. Table 12. CMOS IO buffers generic characteristics
DC Electrical Characteristics All voltages are referenced to VSS, unless otherwise specified, positive current is towards the device Symbol VIL VIH VHY VOL VOH Parameter Low level input voltage High level input voltage Schmitt trigger hysteresis Low level output voltage High level output voltage slow edge < 1 V/ms, only for SCHMITx IOUT = XmA[ IOUT = -XmA[ 0.85*VDD 0.8*VDD 0.8 0.4 Test Conditions Min Typ Max 0.2* VDD Unit V V V V V
The reference current is dependent on the exact buffer chosen and is a part of the buffer name. The available values are 2, 4 and 8 mA. Input/Output TTL Generic Characteristics The values presented in the following table apply for all TTL inputs and/or outputs unless specified otherwise. Table 13. TTL IO buffers generic characteristics
DC Electrical Characteristics All voltages are referenced to VSS, unless otherwise specified, positive current is towards the device Symbol VIL VIH VILHY VIHHY VHY VOL VOH Parameter Low level input voltage High level input voltage Low level threshold, falling High level threshold, rising Schmitt trigger hysteresis Low level output voltage High level output voltage slow edge < 1 V/ms slow edge < 1 V/ms slow edge < 1 V/ms IOUT = XmA[ IOUT = -XmA[ 2.4 2.0 0.9 1.3 0.4 1.35 1.9 0.7 0.4 Test Conditions Min Typ Max 0.8 Unit V V V V V V V
The reference current is dependent on the exact buffer chosen and is a part of the buffer name. The available values are currently 2, 4 and 8 mA. OPERATING CONDITIONS Table 14. Operating Conditions
Maximum ratings Symbol VDD Tamb P Parameter Supply voltage Ambient temperature1m/s airflow Power dissipation Test Conditions Min 3.0 -40 300 Typ 3.3 Max 3.6 +85 400 Unit V C mW
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MTC20136
DIM. MIN. A A1 A2 B C D D1 D3 e E E1 E3 L L1 K 0.65 30.95 27.90 0.25 3.17 0.22 0.13 30.95 27.90
mm TYP. MAX. 4.07 0.010 3.42 3.67 0.38 0.23 31.20 28.00 22.75 0.65 31.20 28.00 22.75 0.80 1.60 0(min.), 7(max.) 0.95 0.026 31.45 28.10 1.219 1.098 31.45 28.10 0.125 0.009 0.005 1.219 1.098 MIN.
inch TYP. MAX. 0.160
OUTLINE AND MECHANICAL DATA
0.135
0.144 0.015 0.009
1.228 1.102 0.896 0.026 1.228 1.102 0.896 0.031 0.063
1.238 1.106
1.238 1.106
0.037
PQFP144
D D1 A D3 A1 108 109 73 72
0.10mm .004 Seating Plane
A2
B
E3
E1
144 1 e 36
37 C
L1
E
L
K
PQFP144
B
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MTC20136
mm DIM. MIN. A A1 A2 b D D1 E E1 e f ddd 0.720 0.650 11.85 0.450 11.85 1.210 0.270 1.120 0.500 12.00 10.40 12.00 10.40 0.800 0.800 0.880 0.950 0.120 0.028 0.025 12.15 0.466 0.550 12.15 0.018 0.466 TYP. MAX. 1.700 MIN. 0.047 0.010
inch TYP. MAX. 0.067
OUTLINE AND MECHANICAL DATA
0.044 0.02 0.472 0.409 0.472 0.409 0.031 0.031 0.034 0.037 0.004 0.478 0.021 0.478
Body: 12 x 12 x 1.7mm
LFBGA160 Low Profile Fine Pitch Ball Grid Array
7254214 A
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MTC20136
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2004 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States www.st.com
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